1. Field of the Invention
The present invention relates to a semiconductor memory device, a semiconductor device including the semiconductor memory device, and a portable electronic apparatus including the semiconductor memory device or the semiconductor device. More specifically, the present invention relates to a semiconductor memory device including a nonvolatile memory cell constructed by field-effect transistors each including a memory functional unit having the function of retaining charges, a semiconductor device including the semiconductor memory device, and a portable electronic apparatus including the semiconductor memory device or the semiconductor device.
2. Description of the Related Art
In general, a microcomputer includes a CPU, a nonvolatile memory and a volatile memory. The nonvolatile memory stores therein a program code and the like, and the volatile memory is used as a work memory. An EEPROM (Electrically Erasable Programmable Read Only Memory) or the like has been conventionally used as the nonvolatile memory.
As an example of the EEPROM, a flash memory will be described below. FIG. 27 is a schematic sectional view showing an example of a flash memory cell. Shown in FIG. 27 are a semiconductor substrate 901, a floating gate 902, a word line (control gate) 903, a diffusion layer source line 904, a diffusion layer bit line 905, a device isolation region 906 and an insulating film 907.
A flash memory cell has a floating gate, and information is held according to an amount of charges in the floating gate. In a memory cell array constructed by arranging memory cells, by selecting a specific word line and a specific bit line and applying a predetermined voltage, an operation of rewriting/reading a desired memory cell can be performed.
FIG. 28 is a graph schematically showing a drain current (Id)-gate voltage (Vg) characteristic when an amount of charges in the floating gate in the flash memory changes. When the amount of negative charges in the floating gate increases, the threshold increases and the Id-Vg curve moves almost in parallel in the Vg increasing direction (see Japanese Unexamined Patent Publication No. Hei 05-304277 (1993)).
However, since the EEPROM includes the floating gate, it has been necessary to pattern two-layered polysilicon in order to form the floating gate and the control gate, thereby causing a complicated process. Therefore, it has been difficult to reduce the cost of the semiconductor memory device including the nonvolatile memory and the volatile memory in addition to the EEPROM per se.